Performance of a large-scale integrated circuit (LSI) has been dramatically improved in terms of capacity, processing speed, and electric power consumption as a result of miniaturization of elements.
However, it is considered that limitation of miniaturization of an element that is based on a conventional operation principle is 0.1 μm. For this reason, researches for a new element based on an operation principle different from the conventional one are now actively conducted. A specific example of such a new element is an element using a quantum wire. The quantum wire is a semiconductor element that is so formed as to have a width as long as the wavelength of the de Broglie wave that is an electron existing in a semiconductor crystal. In cases where a semiconductor is so formed as to have such a width, an electron is confined in the semiconductor layer. This restrains freedom in movement of the electron. Such restriction of the movement of the electron allows a quantum effect. In accordance with the operation principle using this quantum effect, the element using the quantum wire operates.
The quantum wire has a nano meter size cross sectional surface, so that the quantum wire has a new property different from that of a bulk. For example, the quantum wire makes it possible to maintain the phase of an electron wave therein. The electron wave has a wavelength of approximately 10 nm in a semiconductor crystal. Now, think that electrons are generated in a thin-line-like semiconductor (quantum wire) having a rectangular cross sectional surface having a side whose length is approximately 10 nm. In this case, the electrons are hardly dispersed. Hence, each of the electrons is kept within the quantum wire and moves only therein, with the result that the phase of the electron wave is maintained.
One example of usage of such a quantum wire is to use the quantum wire for a transistor. The quantum wire renders the transistor excellent performance. This is specifically explained as follows, for example. That is, a multiplicity of such quantum wires are provided in rows on a substrate, thus forming a gate electrode. Below the gate electrode, a conductive layer for conducting carriers is provided. By controlling an applied voltage to the gate electrode, the number of carriers in the conductive layer is increased or decreased. According to such a structure, it is possible to manufacture a transistor excellent in high-speed operationality and low noise property.
As a conventional and publicly known method for manufacturing a silicon quantum wire, there is a method for growing a silicon quantum wire directly on a silicon substrate in accordance with the VLS (Vapor-Liquid-Solid) method. In this manufacturing method, gold (Au) is deposited on the silicon substrate such that molten alloy drops of silicon and gold are formed on a surface of the silicon substrate, and then supply of a source gas of silicon and heating are carried out simultaneously for the sake of growing the silicon quantum wire.
However, in cases where the VLS method is used, it is difficult to control the size of each molten alloy drop and the formation location thereof. This makes it impossible to form, at equal intervals, silicon quantum wires having the same thickness. This is problematic. Hence, with the conventional technique, it is difficult to provide a multiplicity of quantum wires in rows.
Nano Letters, Vol. 3 , No. 7 (2003) p.p. 951-954 (Citation 1) describes a method for assembling a multiplicity of silicon quantum wires on a substrate having a large area. The method described in Citation 1 uses the Langmuir-Blodget method. In the method, manufactured silicon quantum wires are separated off and are allocated on the substrate having the large area. The use of this method makes it possible to simultaneously assemble the multiplicity of silicon nano wires on electrode locations in a pattern formed on the substrate. In the meanwhile, Japanese Unexamined Patent Publication Tokukai 2005-197612 (published on Jul. 21, 2005) discloses an integrated type quantum wire transistor in which a plurality of silicon nano wires are bound together, and a manufacturing method thereof.
However, the method described in Non-Patent Citation 1 merely makes it possible to simultaneously place the nano wires of one type on the target locations. Meanwhile, Patent Citation 1 does not disclose elements other than the transistor, i.e., elements necessary for actual application as an integrated circuit.